Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Please note that this is valid for the CK804 too.
Values for routing IRQ's:
| Value | APIC Pin (hex.) | APIC Pin (dec.) |
|---|---|---|
| 0x01 | 0x17 | 23 |
| 0x02 | 0x16 | 22 |
| 0x03 | 0x10 | 16 |
| 0x04 | 0x11 | 17 |
| 0x05 | 0x05 | 5 |
| 0x06 | 0x12 | 18 |
| 0x07 | 0x7 | 7 |
| 0x08 | 0x14 | 20 |
| 0x09 | 0x09 | 9 |
| 0x0A | 0x0a | 10 |
| 0x0B | 0x0b | 11 |
| 0x0C | 0x13 | 19 |
| 0x0D | 0x15 | 21 |
| 0x0E | 0x0E | 14 |
| 0x0F | 0x0F | 15 |
Each line is 4 bits.
| 0x7c | 0x80 | 0x84 |
|---|---|---|
| INTA | SCII | INTG |
| INTB | TCOI | INTH |
| INTC | INTF | INTJ |
| INTD | INTQ | INTK |
| PCEA | INTU | INTL |
| PCEB | INTS | INTM |
| PCEC | IS0P | INTN |
| PCED | ITID | ISA2 |
| Device/Pin | Routed to Pin | Description |
|---|---|---|
| 1/INTA | INTF | ISALPC |
| 1/INTB | INTS | SMBus |
| 2/INTA | INTG | Usb0 |
| 2/INTB | INTQ | Usb1 |
| 4/INTA | INTN | IDE |
| 5/INTA | ITID | Sata1 |
| 5/INTB | IS0P | Sata2 |
| 5/INTC | ISA2 | Sata3 |
| 6/INTA | INTU | Bridge to Bus 1 |
| 6/INTB | INTK | Audio |
| 8/INTA | INTJ | Ethernet |
Bridges to the PCI-E Slots & Devices
| Device/Pin | Routed to Pin | Description |
|---|---|---|
| F/INTA | PCEB | Bridge to Bus 7 - PCIE 16x (black) |
| F/INTB | PCEC | |
| F/INTC | PCED | |
| F/INTD | PCEA | |
| E/INTA | PCEC | Bridge to Bus 6 |
| E/INTB | PCED | |
| E/INTC | PCEA | |
| E/INTD | PCEB | |
| D/INTA | PCED | Bridge to Bus 5 |
| D/INTB | PCEA | |
| D/INTC | PCEB | |
| D/INTD | PCEC | |
| C/INTA | PCEA | Bridge to Bus 4 |
| C/INTB | PCEB | |
| C/INTC | PCEC | |
| C/INTD | PCED | |
| B/INTA | PCEB | Bridge to Bus 3 |
| B/INTB | PCEC | |
| B/INTC | PCED | |
| B/INTD | PCEA | |
| A/INTA | PCEC | Bridge to Bus 2 - PCIE 16x (blue) |
| A/INTB | PCED | |
| A/INTC | PCEA | |
| A/INTD | PCEB |
Bus 1 behind bridge from device 6
| Device/Pin | Routed to Pin | Description |
|---|---|---|
| 6/INTA | INTC | |
| 6/INTB | INTD | |
| 6/INTC | INTA | |
| 6/INTD | INTB | |
| 7/INTA | INTD | PCI Slot 1 |
| 7/INTB | INTA | |
| 7/INTC | INTB | |
| 7/INTD | INTC | |
| 8/INTA | INTA | PCI Slot 2 |
| 8/INTB | INTB | |
| 8/INTC | INTC | |
| 8/INTD | INTD | |
| 9/INTA | INTB | |
| 9/INTB | INTC | |
| 9/INTC | INTD | |
| 9/INTD | INTA | |
| A/INTA | INTC | |
| A/INTB | INTD | |
| A/INTC | INTA | |
| A/INTD | INTB |
This source is to do a propper mptable setup on M57SLI.
Setup the registers 0x7c-0x84 with the IRQ Values you want to have:
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
}
dword = 0xc643c643;
pci_write_config32(dev, 0x7c, dword);
dword = 0x8da01009;
pci_write_config32(dev, 0x80, dword);
dword = 0x200018d2;
pci_write_config32(dev, 0x84, dword);
}
}
According to the Registers 0x7c-0x84 do the IRQ setup:
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
PCI_INT(0,sbdn+1,1, 10); /* SMBus */
PCI_INT(0,sbdn+2,0, 22); /* USB */
PCI_INT(0,sbdn+2,1, 23); /* USB */
PCI_INT(0,sbdn+4,0, 21); /* IDE */
PCI_INT(0,sbdn+5,0, 20); /* SATA */
PCI_INT(0,sbdn+5,1, 21); /* SATA */
PCI_INT(0,sbdn+5,2, 22); /* SATA */
PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
PCI_INT(1,0x0a,0, 18); /* Firewire */
/* The PCIe slots, each on its own bus */
k = 1;
for(i=0; i<=3; i++){
for(j=7; j>=2; j--){
if(k>3) k=0;
PCI_INT(j,0,i, 16+k);
k++;
}
k--;
}
/* On bus 1: the PCI bus slots... */
k=2;
for(i=0; i<=3; i++){
for(j=6; j<=10; j++){
if(k>3) k=0;
PCI_INT(1,j,i, 16+k);
k++;
}
}
For this the registers 0x7c-0x84 need to be set so that this static routing will work.
/* PCI Routing Table */
Name (_PRT, Package () {
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
})
Device (PEBA) /* PCI-E Bridge A */
{
Name (_ADR, 0x000A0000)
Name (_UID, 0x00)
Name (_BBN, 0x02)
Name (_Prt, Package () {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
})
}
Bridge B-F needs also to get a routing setting, but not listed here.
Device (PCID) /* PCI Device */
{
Name (_ADR, 0x00060000)
Name (_UID, 0x00)
Name (_BBN, 0x01)
Name (_PRT, Package () {
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 },
Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 },
Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
})
}
... go to Rudolf Marek who figured the informations out from the M57SLI's vendor dsdt.asl, and while he was doing this on a train his wallet was stolen. So please keep that informations careful, it's valuable. :)