Cpu:allwinner/a10: Difference between revisions
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| Line 6: | Line 6: | ||
| | AXI Div | | AHB Div | | APB0 Div | | | | | AXI Div | | AHB Div | | APB0 Div | | | ||
| CPU clock |------------>| AXI clock |------------>| AXI clock |------------->| APB0 clock | | | CPU clock |------------>| AXI clock |------------>| AXI clock |------------->| APB0 clock | | ||
| | | | 1,2,3,4 | 350M max | 1,2,4,8 | 250M max | 2,2,4,8 | 150M max | | ||
|___________| |___________| |___________| |____________| | |||
Revision as of 02:07, 11 January 2014
This is meant as a quick might-need-to-know page for Allwinner A10 (and potentially A13 and later) SoCs
Clock structure
___________ ___________ ___________ ____________ | | AXI Div | | AHB Div | | APB0 Div | | | CPU clock |------------>| AXI clock |------------>| AXI clock |------------->| APB0 clock | | | 1,2,3,4 | 350M max | 1,2,4,8 | 250M max | 2,2,4,8 | 150M max | |___________| |___________| |___________| |____________|