HP COMPAQ NC6320

Status

Nothing work yet, no output on serial.

Hardware

• CPU: T7200
• Northbridge: 945GM
• Southbridge: ICH7-M
• superio: SMSC LPC47N217
• ec: SMSC LPC47N217
• flash chip: M25PE80,1024 kB, soldered,SOIC-8

How to flash

• disassemble the laptop
• Put the power adapter in the laptop's power plug
• power off the laptop
• attach the pomona clip and flash(backup the BIOS before.)

how to unpack the BIOS

See http://paste.flashrom.org/view.php?id=1523

Ec Issue

The ec firmware(4000_KBC.bin) probably has to be in the image at the same fixed position than the BIOS.

Patch (not working)

The nc6320 is very similar to the Roda rk886ex, with only the superio that is different.

From 2e933fe48332af46a8c19394d0e987f31ba24334 Mon Sep 17 00:00:00 2001
From: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date: Mon, 14 Jan 2013 00:28:07 +0100
Subject: [PATCH] Changes for nc6320

Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
---
 src/mainboard/roda/rk886ex/Kconfig       |  2 +-
 src/mainboard/roda/rk886ex/devicetree.cb |  2 +-
 src/mainboard/roda/rk886ex/romstage.c    | 67 ++++++--------------------------
 3 files changed, 14 insertions(+), 57 deletions(-)

diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 84a8543..0095f4d 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 	select SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_TI_PCI7420
-	select SUPERIO_SMSC_LPC47N227
+	select SUPERIO_SMSC_LPC47N217
 	select SUPERIO_RENESAS_M3885X
 	select EC_ACPI
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index aadba9d..955561a 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/intel/i945
 			#device pci 1e.2 off end # AC'97 Audio
 			#device pci 1e.3 off end # AC'97 Modem
                         device pci 1f.0 on # LPC bridge
-                                chip superio/smsc/lpc47n227
+                                chip superio/smsc/lpc47n217
 					device pnp 2e.1 on # Parallel port
 						 io 0x60 = 0x378
 						irq 0x70 = 5
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index d75d33f..b2ebce0 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -35,6 +35,7 @@
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
+#include "superio/smsc/lpc47n217/early_serial.c"
 #include "option_table.h"
 
 void setup_ich7_gpios(void)
@@ -87,63 +88,19 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
 }
 
-/* This box has two superios, so enabling serial becomes slightly excessive.
- * We disable a lot of stuff to make sure that there are no conflicts between
- * the two. Also set up the GPIOs from the beginning. This is the "no schematic
- * but safe anyways" method.
- */
-static inline void pnp_enter_ext_func_mode(device_t dev)
-{
-	unsigned int port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	unsigned int port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void pnp_write_register(device_t dev, int reg, int val)
-{
-	unsigned int port = dev >> 8;
-	outb(reg, port);
-	outb(val, port+1);
-}
-
+/* Found SMSC LPC47N217 (id=0x7a, rev=0x01) at 0x4e */
+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 static void early_superio_config(void)
 {
-	device_t dev;
-
-	dev=PNP_DEV(0x2e, 0x00);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
-	pnp_write_register(dev, 0x02, 0x88); // UART power on
-	pnp_write_register(dev, 0x03, 0x72); // Floppy
-	pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
-	pnp_write_register(dev, 0x14, 0x03); // Floppy
-	pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
-	pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
-	pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
-	pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
-	pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
-	pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
-	pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
-	/* These are the SMI status registers in the SIO: */
-	pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
-
-	pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
-	pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
-	pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
-	pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
-	pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
-	pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
-	pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
-	pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
-	pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
-
-	pnp_exit_ext_func_mode(dev);
+	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+#if 0
+	outb(0x24, 0xcd6);
+	outb(0x1, 0xcd7);
+	outb(0xea, 0xcd6);
+	outb(0x1, 0xcd7);
+	*(u8 *)0xfed80101 = 0x98;
+#endif
 }
 
 static void rcba_config(void)
-- 
1.8.1